Hardware Architecture for Realtime HEVC Intra Prediction

Researchers have, in recent times, achieved excellent compression efficiency by implementing a more complicated algorithm due to the rapid development of video compression. As result, next model compression, High-Efficiency Video Coding (HEVC), provides high-quality output while requiring less bandwidth. However, intra-prediction technique HEVC requires significant processing complexity. This research completely pipelined hardware architecture solution capable real-time minimize computing All prediction unit sizes 4×4, 8×8, 16×16, and 32×32, all planar, angular, DC modes are supported proposed solution. The synthesis results mapped Xilinx Virtex 7 reveal that our can do with 210 frames per second (FPS) at 1920×1080 resolution, called Full High Definition (FHD), or 52 FPS 3840×2160 4K, operating 232 Mhz maximum frequency.